View ICS8752BYLF_8071882.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

8752 www.icst.com/products/hiperclocks.html rev. b may 4, 2001

ics8752 l ow s kew 1- to -8 lvcmos c lock m ultiplier /z ero d elay b uffer preliminary b lock d iagram p in a ssignment 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 gnd qb1 qb0 vddo vddo qa3 qa2 gnd div_selb0 div_selb1 div_sela0 div_sela1 mr/noe ref_clk1 gnd fb_in vddo qa1 qa0 gnd ref_clk2 vddi vdda clk_sel vddo qb2 qb3 gnd gnd nc pll_sel vddi ics8752 32-lead lqfp y package to p vi e w 2 4 6 8 12 pll phase detector pll_sel fb_in ref_clk1 ref_clk2 clk_sel div_sela1 div_sela0 div_selb1 div_selb0 mr/noe qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 0 1 1 0 00 01 10 11 00 01 10 11 vco the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specific ations without notice. g eneral d escription the ics8752 is a low voltage, low skew clock generator and a member of the hiperclocks? family of high performance clock solutions from ics. with output frequencies up to 240mhz the ics8752 is targeted for high performance clock applications. along with a fully integrated pll the ics8752 contains frequency configurable outputs and an external feedback input for regenerating clocks with ?zero de- lay?. dual clock inputs, ref_clk1 and ref_clk2, support redundant clock applications. the clk_sel input determines which reference clock is used. the output divider values of bank a and b are controlled by the div_sela0:1, and div_selb0:1, respectively. for test and system debug purposes the pll_sel input allows the pll to be bypassed. when high the mr/noe input resets the internal dividers and forces the outputs to the high impedance state. the low impedance lvcmos outputs of the ics8752 are designed to drive terminated transmission lines. the effec- tive fanout of each output can be doubled by utilizing the ability of each output to drive two series terminated trans- mission lines. f eatures ? fully integrated pll ? 8 lvcmos outputs, 7 ? typical output impedance ? external feedback for ?zero delay? clock regeneration ? output frequency up to 240mhz ? vco range 220mhz to 480mhz ? dual lvcmos clock inputs for redundant clock applications ? lvcmos control inputs ? bank skew, tsk(b), 100ps ? output skew, tsk(o), 150ps ? multiple-frequency skew, tsk(w), 200ps ? cycle-to-cycle jitter, tjit(cc), 100ps, typical ? pll reference zero delay, t(?), 150ps, typical ? full 3.3v ? 32 lead low-profile qfp (lqfp) ? 7mm x 7mm x 1.4mm package body, 0.8mm lead pitch ? 0c to 70c ambient operating temperature ? functionally compatible with the mpc952 in some applications hiperclocks?
8752 www.icst.com/products/hiperclocks.html rev. b may 4, 2001 2

ics8752 l ow s kew 1- to -8 lvcmos c lock m ultiplier /z ero d elay b uffer preliminary t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 1 , 0 b l e s _ v i d 1 b l e s _ v i d t u p n in w o d l l u p . 3 e l b a t n i d e b i r c s e d s a b k n a b r o f s e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 4 , 3 , 0 a l e s _ v i d 1 a l e s _ v i d t u p n in w o d l l u p . 3 e l b a t n i d e b i r c s e d s a a k n a b r o f s e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 5e o n / r mt u p n in w o d l l u p . e t a t s e c n a d e p m i h g i h o t n i t u p t u o s e c r o f d n a s r e d i v i d s t e s e r , h g i h n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l 61 k l c _ f e rt u p n in w o d l l u p. s l e v e l e c a f r e t n i s o m c v l . t u p n i k c o l c e c n e r e f e r 3 1 , 7 , 4 2 , 7 1 9 2 , 8 2 d n gr e w o p. d n u o r g o t t c e n n o c . n i p d n u o r g 8n i _ b ft u p n in w o d l l u p . " y a l e d o r e z " h t i w s k c o l c g n i t a r e n e g e r r o f r o t c e t e d e s a h p o t t u p n i k c a b d e e f . s l e v e l e c a f r e t n i l t t v l / s o m c v l 9l e s _ k l ct u p n in w o d l l u p . e c n e r e f e r r o t c e t e d e s a h p s a 2 k l c _ f e r r o 1 k l c _ f e r n e e w t e b s t c e l e s . 2 k l c _ f e r s t c e l e s h g i h n e h w . 1 k l c _ f e r s t c e l e s w o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l 0 1a d d vr e w o p. v 3 . 3 o t t c e n n o c . n i p y l p p u s r e w o p l l p 2 3 , 1 1i d d vr e w o p. v 3 . 3 o t t c e n n o c . n i p y l p p u s r e w o p e r o c d n a t u p n i 2 12 k l c _ f e rt u p n in w o d l l u p. s l e v e l e c a f r e t n i s o m c v l . t u p n i k c o l c e c n e r e f e r , 5 1 , 4 1 9 1 , 8 1 , 1 a q , 0 a q 3 a q , 2 a q t u p t u o . s t u p t u o k c o l c a k n a b7 ? . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i s o m c v l , 0 2 , 6 1 5 2 , 1 2 o d d vr e w o p. v 3 . 3 o t t c e n n o c . s n i p y l p p u s r e w o p t u p t u o , 3 2 , 2 2 7 2 , 6 2 , 1 b q , 0 b q 3 b q , 2 b q t u p t u o . s t u p t u o k c o l c b k n a b7 ? . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i s o m c v l 0 3c nd e s u n u. n i p d e s u n u 1 3l e s _ l l pt u p n ip u l l u p e h t o t t u p n i e h t s a k c o l c e c n e r e f e r e h t d n a l l p e h t n e e w t e b s t c e l e s . k c o l c e c n e r e f e r s t c e l e s w o l n e h w . l l p t c e l e s h g i h n e h w . s r e d i v i d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 2 3i d d vr e w o p. v 3 . 3 o t t c e n n o c . n i p y l p p u s r e w o p t u p n i
8752 www.icst.com/products/hiperclocks.html rev. b may 4, 2001

ics8752 l ow s kew 1- to -8 lvcmos c lock m ultiplier /z ero d elay b uffer preliminary t able 2. p in c haracteristics t able 3. c ontrol i nputs f unction t able l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n i c t u p n i e c n a t i c a p a c , 1 k l c _ f e r 2 k l c _ f e r d b tf p , l e s _ l l p , n i _ b f l e s _ k l c , 1 a l e s _ v i d , 0 a l e s _ v i d , 1 b l e s _ v i d 0 b l e s _ v i d d b tf p p u l l u p r t u p n i r o t s i s e r p u l l u p 1 5k ? n w o d l l u p r t u p n i n w o d l l u p r o t s i s e r 1 5k ? d p c n o i t a p i s s i d r e w o p e c n a t i c a p a c ) t u p t u o r e p ( v 7 4 . 3 = o d d v , i d d v , a d d vd b tf p t u o r t u p t u o e c n a d e p m i 7 ? s t u p n is t u p t u o e o n / r ml e s _ l l pl e s _ k l c _ v i d 1 a l e s _ v i d 0 a l e s _ v i d 1 b l e s _ v i d 0 b l e s x a qx b q 1xxxxxx z - i hz - i h 01x0000 2 / o c v f4 / o c v f 01x 0 1 0 1 4 / o c v f6 / o c v f 01x 1 0 1 0 6 / o c v f8 / o c v f 01x1111 8 / o c v f2 1 / o c v f 0000000 2 / 1 k l c _ f e r f4 / 1 k l c _ f e r f 00 0 0 1 0 1 4 / 1 k l c _ f e r f6 / 1 k l c _ f e r f 00 0 1 0 1 0 6 / 1 k l c _ f e r f8 / 1 k l c _ f e r f 0001111 8 / 1 k l c _ f e r f2 1 / 1 k l c _ f e r f 0010000 2 / 2 k l c _ f e r f4 / 2 k l c _ f e r f 00 1 0 1 0 1 4 / 2 k l c _ f e r f6 / 2 k l c _ f e r f 00 1 1 0 1 0 6 / 2 k l c _ f e r f8 / 2 k l c _ f e r f 0011111 8 / 2 k l c _ f e r f2 1 / 2 k l c _ f e r f . d e l b a s i d e r a s t u p u o l l a h g i h s i e o n / r m n e h w . w o l s i e o n / r m n o i t a r e p o l a m r o n r o f : e t o n
8752 www.icst.com/products/hiperclocks.html rev. b may 4, 2001 4

ics8752 l ow s kew 1- to -8 lvcmos c lock m ultiplier /z ero d elay b uffer preliminary t able 4a. qa o utput f requency w /fb_in = qb s t u p n it u p t u o n i _ b f1 b l e s _ v i d0 b l e s _ v i d b q t u p u o r e d i v i d e d o m , 1 k l c _ f e r 2 k l c _ f e r ) z h m ( 1 a l e s _ v i d0 a l e s _ v i d a q t u p u o r e d i v i d e d o m a q r e i l p i t l u m ) 1 e t o n ( n i mx a m b q0 0 4 5 . 2 65 2 1 00 2 2 01 4 1 10 6 7 6 6 . 0 11 8 5 . 0 b q0 1 6 7 6 . 1 43 3 . 3 8 00 2 3 01 4 5 . 1 10 6 1 11 8 5 7 . 0 b q1 0 8 5 2 . 1 35 . 2 6 00 2 4 01 4 2 10 6 3 3 . 1 11 8 1 b q1 1 2 1 3 8 . 0 27 6 . 1 4 01 2 6 01 4 3 10 6 2 11 8 5 . 1 . z h m 0 0 5 o t z h m 0 5 2 s i e g n a r y c n e u q e r f o c v : 1 e t o n : 1 e t o n ; r e i l p i t l u m e h t s e m i t y c n e u q e r f k c o l c e c n e r e f e r o t l a u q e y c n e u q e r f t u p t u o a q : 2 e t o n . k c o l c e c n e r e f e r o t l a u q e y c n e u q e r f t u p t u o b q
8752 www.icst.com/products/hiperclocks.html rev. b may 4, 2001

ics8752 l ow s kew 1- to -8 lvcmos c lock m ultiplier /z ero d elay b uffer preliminary t able 4b. qb o utput f requency w /fb_in = qa t able 5. pll i nput r eference c haracteristics , vddi=vdda=3.3v5%, t a =0 c to 70 c s t u p n it u p t u o n i _ b f1 a l e s _ v i d0 a l e s _ v i d a q t u p u o r e d i v i d e d o m , 1 k l c _ f e r 2 k l c _ f e r ) z h m ( 1 b l e s _ v i d0 b l e s _ v i d b q t u p u o r e d i v i d e d o m b q r e i l p i t l u m ) 2 e t o n ( n i mx a m a q0 0 2 5 2 10 5 2 00 4 5 . 0 01 6 3 3 3 . 0 10 8 5 2 . 0 11 2 1 3 8 0 . 0 a q0 1 4 5 . 2 65 2 1 00 4 1 01 6 7 6 6 . 0 10 8 5 . 0 11 2 1 3 3 3 . 0 a q1 0 6 7 6 . 1 43 3 . 3 8 00 4 5 . 1 01 6 1 10 8 5 7 . 0 11 2 1 5 . 0 a q1 1 8 5 2 . 1 35 . 2 6 01 4 2 01 6 3 3 3 . 1 10 8 1 11 2 1 7 6 6 . 0 . z h m 0 0 5 o t z h m 0 5 2 s i e g n a r y c n e u q e r f o c v : 1 e t o n ; r e i l p i t l u m e h t s e m i t y c n e u q e r f k c o l c e c n e r e f e r o t l a u q e y c n e u q e r f t u p t u o b q : 2 e t o n . k c o l c e c n e r e f e r o t l a u q e y c n e u q e r f t u p t u o a q l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f e r fy c n e u q e r f e c n e r e f e r t u p n i0 20 4 2z h m r te m i t e s i r t u p n is t n i o p % 0 8 o t % 0 2 t a d e r u s a e md b ts n f te m i t l l a f t u p n it n i o p % 0 8 o t % 0 2 t a d e r u s a e md b ts n c d te l c y c y t u d e c n e r e f e r t u p n id b td b t%
8752 www.icst.com/products/hiperclocks.html rev. b may 4, 2001 6

ics8752 l ow s kew 1- to -8 lvcmos c lock m ultiplier /z ero d elay b uffer preliminary t able 6b. lvcmos/lvttl dc c haracteristics , vddi=vdda=vddo=3.3v5%, t a =0 c to 70 c t able 6a. p ower s upply dc c haracteristics , vddi=vdda=vddo=3.3v5%, t a =0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i d d ve g a t l o v y l p p u s r e w o p t u p n i 5 3 1 . 33 . 35 6 4 . 3v a d d ve g a t l o v y l p p u s r e w o p g o l a n a 5 3 1 . 33 . 35 6 4 . 3v o d d ve g a t l o v y l p p u s r e w o p t u p t u o 5 3 1 . 33 . 35 6 4 . 3v d d it n e r r u c y l p p u s r e w o p t u p n i 0 7a m a bsolute m aximum r atings supply voltage 4.6v inputs -0.5v to vdd+0.5 v outputs -0.5v to vdd+0.5v ambient operating temperature 0 c to 70 c storage temperature -65 c to 150 c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any conditions beyond those listed in the dc character- istics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u h i ve g a t l o v h g i h t u p n i 25 6 7 . 3v l i ve g a t l o v w o l t u p n i 3 . 0 -8 . 0v h i it n e r r u c h g i h t u p n i 2 k l c _ f e r , 1 k l c _ f e r , l e s _ k l c , n i _ b f , 0 a l e s _ v i d , 1 a l e s _ v i d , 0 b l e s _ v i d , 1 b l e s _ v i d e o n / r m v 5 6 4 . 3 = n i v0 5 1a l e s _ l l pv 5 6 4 . 3 = n i v5a l i it n e r r u c w o l t u p n i 2 k l c _ f e r , 1 k l c _ f e r , l e s _ k l c , n i _ b f , 0 a l e s _ v i d , 1 a l e s _ v i d , 0 b l e s _ v i d , 1 b l e s _ v i d e o n / r m v 0 = n i v5 -a l e s _ l l pv 0 = n i v0 5 1 -a h o ve g a t l o v h g i h t u p t u o v 5 3 1 . 3 = o d d v a m 6 3 - = h o i 6 . 2v l o ve g a t l o v w o l t u p t u o v 5 3 1 . 3 = o d d v a m 6 3 = l o i 5 . 0v
8752 www.icst.com/products/hiperclocks.html rev. b may 4, 2001

ics8752 l ow s kew 1- to -8 lvcmos c lock m ultiplier /z ero d elay b uffer preliminary t able 7. ac c haracteristics , vddi=vdda=vddo=3.3v5%, t a =0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u x a m fy c n e u q e r f t u p t u o m u m i x a m 2 0 4 2z h m 4 0 2 1z h m 6 0 8z h m 8 0 6z h m 1 2 0 4z h m fo c ve g n a r k c o l o c v l l p 0 4 20 8 4z h m h l p th g i h - o t - w o l , y a l e d n o i t a g a p o r p , v 0 = l e s _ l l p z h m 0 f z h m 0 4 2 d b td b ts n l h p tw o l - o t - h g i h , y a l e d n o i t a g a p o r p , v 0 = l e s _ l l p z h m 0 f z h m 0 4 2 d b td b ts n ) ? ( t ; y a l e d o r e z e c n e r e f e r l l p 2 e t o n , d b t = f e r f , v 3 . 3 = l e s _ l l p d b t = o c v f 0 5 1 s p ) b ( k s t3 e t o n ; w e k s k n a b a k n a b t a e g d e g n i s i r n o d e r u s a e m 2 / o d d v 5 7s p b k n a b 0 0 1s p ) o ( k s t4 e t o n ; w e k s t u p t u o t a e g d e g n i s i r n o d e r u s a e m 2 / o d d v 0 5 1s p ) w ( k s t ; w e k s y c n e u q e r f e l p i t l u m 5 e t o n t a e g d e g n i s i r n o d e r u s a e m 2 / o d d v 0 0 2s p ) c c ( t i j t6 e t o n ; r e t t i j e l c y c - o t - e l c y c 0 0 1s p ) ? ( t i j tr e t t i j e s a h p 0 5 1s p l te m i t k c o l l l p 1s m r te m i t e s i r t u p t u o% 0 8 o t % 0 20 0 30 0 8s p f te m i t l l a f t u p t u o% 0 8 o t % 0 20 0 30 0 8s p w p th t d i w e s l u p t u p t u o z h m 0 f z h m 0 4 2 2 / e l c y c t 0 0 5 - 2 / e l c y c t 2 / e l c y c t 0 0 5 + s p z h m 0 2 1 = f5 6 . 30 . 45 3 . 4s n n e te m i t e l b a n e t u p t u o d b ts n s i d te m i t e l b a s i d t u p t u o d b ts n 0 5 h t i w d e t a n i m r e t s t u p t u o l l a . e s i w r e h t o d e t o n s s e l n u x a m f t a d e r u s a e m s r e t e m a r a p l l a : 1 e t o n ? . 2 / o d d v o t l a n g i s t u p n i k c a b d e e f d e g a r e v a e h t d n a k c o l c e c n e r e f e r t u p n i e h t n e e w t e b e c n e r e f f i d e m i t e h t s a d e n i f e d : 2 e t o n . e l b a t s s i y c n e u q e r f e c n e r e f e r t u p n i e h t d n a d e k c o l s i l l p e h t n e h w . s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a s t u p t u o f o k n a b a n i h t i w w e k s s a d e n i f e d : 3 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a s t u p t u o f o s k n a b s s o r c a w e k s s a d e n i f e d : 4 e t o n s e g a t l o v y l p p u s e m a s e h t h t i w y c n e u q e r f t n e r e f f i d t a g n i t a r e p o s t u p t u o f o s k n a b s s o r c a w e k s s a d e n i f e d : 5 e t o n . s n o i t i d n o c d a o l l a u q e d n a t n e c a j d a f o e l p m a s m o d n a r a r e v o , s e l c y c t n e c a j d a n e e w t e b l a n g i s a f o e m i t e l c y c n i n o i t a i r a v e h t s a d e n i f e d : 6 e t o n . s e l c y c f o s r i a p
8752 www.icst.com/products/hiperclocks.html rev. b may 4, 2001 8

ics8752 l ow s kew 1- to -8 lvcmos c lock m ultiplier /z ero d elay b uffer preliminary p ackage o utline - y s uffix e e1 d1 d ccc c seating plane d2 -c- e2 e a n a1 a2 b c l 916 1 2 3 817 24 32 25 t able 8. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 q 0 - - 7 c c c - -- -0 1 . 0
8752 www.icst.com/products/hiperclocks.html rev. b may 4, 2001

ics8752 l ow s kew 1- to -8 lvcmos c lock m ultiplier /z ero d elay b uffer preliminary t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t y b 2 5 7 8 s c iy b 2 5 7 8 s c ip f q l d a e l 2 3y a r t r e p 0 5 2c 0 7 o t c 0 t y b 2 5 7 8 s c iy b 2 5 7 8 s c il e e r d n a e p a t n o p f q l d a e l 2 30 0 0 1c 0 7 o t c 0

▲Up To Search▲

Price & Availability of ICS8752BYLF

	To Download ICS8752BYLF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .